πR²: Reactive Real-time Flow Policies

ListenFast Hands, Slow Eyes: Making Flow Policies React10:04

Show notes

A look at πR², which retrofits large flow-matching robot policies so they replan closed-loop at roughly 25 Hz on an A5000 — about 4× faster than the base GR00T-N1.7 policy — without shrinking the backbone. The trick is two structural changes: split conditioning into a fast proprioception channel and a slow, asynchronously-updated vision-language channel, and use a latency-adaptive per-position noise schedule that emits clean actions in a single denoising step per call. On four contact-rich dexterous tasks it beats the strongest baseline, Train-Time RTC, by up to ~30% absolute success rate. **Sources** - πR²: Reactive Real-time Flow Policies

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TL;DR

πR² retrofits large flow-matching VLAs (evaluated on GR00T-N1.7) with two changes that together push closed-loop replanning to ~25 Hz on an A5000 GPU — roughly 4× faster than the base policy — while keeping the backbone, action-chunking, and expressive multi-modal output distribution intact. First, it disentangles conditioning into a slow channel (image + language features from the VLM, updated asynchronously in a background thread) and a fast channel (proprioception, refreshed every control tick). Second, it uses a latency-adaptive per-position noise schedule — a three-region staircase over the chunk (clamped-clean front for in-flight actions, ramped interior, pure-noise tail) parameterized by the measured inference delay τ, letting one trained model absorb varying latency and emit clean actions in a single denoising step per call. On four contact-rich real-world dexterous tasks (xArm6 + XHand), πR² beats the strongest baseline (Train-Time RTC) by up to ~30% absolute success rate, with the largest gains on tasks where fingertip-force reactivity matters (Tidy Up Book, Catch Book).

Key claims

Action-chunking flow VLAs suffer two coupled problems — reduced reactivity (open-loop execution during chunk) and increased latency (stale sensory input) — and predicting a smaller sub-chunk to restore reactivity is infeasible because the VLM backbone + multi-step denoising dominates per-call latency [§1].
The vision/language pathway can be updated at a much lower rate than proprioception without losing manipulation quality — vision/language provide global spatial and task guidance, while fresh proprioception drives local reactive corrections (contact response, slip compensation) [§3.2].
Running the DiT action head with one denoising step per call (rather than K steps) suffices when the front of the chunk is kept near noise level τ=0 via diffusion forcing; per-call action-head cost is 1 NFE, independent of backbone size [§3.2].
A learned delay embedding — the integer τ indexed into a lookup table and added to the slow-channel representation — lets one model absorb bounded VLM-feature staleness without a separate policy per delay setting [§3.2].
The latency-adaptive staircase noise schedule is a strict generalization of Train-Time RTC’s inpaint-conditioning [Kevin Black et al., arxiv:2512.05964]: RTC uses one shared noise level over the non-clamped positions; πR² replaces that with a linear ramp plus a pure-noise tail so a single denoising step per call emits M new clean actions where M ≥ 1 depends on τ [§3.3, Eq. 3].
Training samples τ per batch and applies symmetric jitter to absorb per-call variation; with probability p a standard shared-τ flow schedule is used instead so the same network can warm-start the buffer at episode start [§3.3].
The AdaLN conditioning in a DiT action head becomes per-position (one (γ, β) pair per chunk position) rather than shared across positions — the one-line architectural change that makes πR² a drop-in fine-tune on any pretrained flow-matching VLA [§3.3].
On the Leap Cube Reorientation MuJoCo Playground task at zero inference delay, πR² with 1 NFE per call matches standard flow-matching with K=10 denoising steps and horizon H=1, and both beat larger execution horizons — amortizing denoising across calls doesn’t sacrifice reactivity [§4.1.1, Fig. 3 left].
Under a realistic GR00T-N1.7 latency budget (image + VLM ≈ 100 ms, one NFE ≈ 5 ms, unit delay = one NFE), πR² with async fast/slow processing wins at every measured τ (baselines 0.86/0.83/0.80; πR² 0.98/0.97/0.96 at τ = 1/3/5), with the gap widening as delay grows [§4.1.2, Fig. 3 right].
Real-world results (xArm6 + XHand, four dexterous tasks, RTX A5000): πR² beats Flow Synchronous / Naive Async+TE / Train-Time RTC on both success rate and per-task progress; largest lifts on the reactivity-critical tasks — Tidy Up Book (12/20 SR vs RTC’s 8/20), Catch Book (11/20 vs 5/20), Insert Box (16/20 vs 10/20) [§4.2, Table 1].
Qualitatively, πR²’s per-tick proprioceptive refresh lets it modulate grip force off live fingertip contact — on Tidy Up Book it stops near 50 N (just enough to reorient the book), while Train-Time RTC commits to a stale plan and overshoots to 120 N, crushing the book [§4.2, Fig. 5].

Method

The base VLA is GR00T-N1.7: image + text pass through a vision-language backbone (image preprocessing + VLM ≈ 100 ms), proprioception passes through a small MLP into a state embedding, and a DiT action head runs K denoising steps over an H-length action chunk conditioned on the concatenation. πR² makes two changes.

(1) Proprioception-Reactive Diffusion Forcing (§3.2). The DiT is re-conditioned in two channels. The slow channel (image + language) is computed in a background thread and its output is cached; a learned integer-delay embedding (indexed by the number of ticks τ since the cache was refreshed) is added to the cached slow representation. The fast channel (proprioception) is re-read every control tick. The DiT runs a single denoising step per call against the fresh proprioception and the cached (possibly stale) slow feature. Per-call action-head cost becomes 1 NFE regardless of backbone size, and the slow channel updates whenever a background VLM forward completes.

(2) Latency-Adaptive Flow Schedule (§3.3). A per-position noise schedule σ_i(t; τ) parameterized by the measured inference delay τ imposes a three-region staircase over the H-position chunk: a clean front carrying in-flight actions as inpaint conditioning (analogous to Train-Time RTC but as a limiting case of a more flexible schedule), a linearly ramped interior that produces M new clean actions per call at the cost of one denoising step, and a pure-noise tail appended each cycle. At training τ is sampled uniformly plus symmetric jitter so a single network handles a range of measured latencies; a probability-p mixed-in standard flow schedule allows the same network to also warm-start from pure noise at episode start. Architecturally, this only requires making the DiT’s AdaLN conditioning per-position rather than shared across positions.

At inference each call applies one denoising step to update every position, emits the M positions that reach t=0, rotates the buffer forward by M, and appends M fresh-noise slots. When τ changes between calls the schedule adapts to the new value over a few calls.

Results

MuJoCo Playground Leap Cube Reorientation, zero-delay sweep (Fig. 3 left): standard flow at H=1, K=10 tops the baseline (~0.98 success); πR² with 1 NFE per call matches it. Larger H values degrade steadily.
MuJoCo Playground under VLA-level latency (Fig. 3 right): effective per-call delay for baselines is τ=100 ms + K·5 ms = 150 ms; πR² without async processing pays 5 ms per call; πR² with async pays only 5 ms for the action loop while the visual delay grows separately. At τ = 1/3/5 unit-delay ticks, πR² w/ async reports (0.98, 0.97, 0.96) vs Train-Time RTC (0.86, 0.83, 0.80) vs Naive Async (0.72, 0.65, 0.59).
Real-world (xArm6 + XHand, four tasks, per-tick 40 ms, RTX A5000, Table 1):
- Don’t Spill: πR² 10/20 (progress 55/80) vs Train-Time RTC 9/20 (45/80) vs Naive Async 7/20 vs Flow Sync 4/20.
- Tidy Up Book: πR² 12/20 (24/40) vs RTC 8/20 (18/40) vs Naive Async 7/20 vs Sync 4/20.
- Insert Box: πR² 16/20 (68/80) vs RTC 10/20 (53/80) vs Naive Async 12/20 vs Sync 11/20.
- Catch Book: πR² 11/20 vs RTC 5/20 vs Sync 4/20 vs Naive Async 2/20.
Reactivity mechanism (Fig. 5): on Tidy Up Book, πR² modulates grip force off live fingertip contact and stops near 50 N; Train-Time RTC commits to a stale plan, overshoots to 120 N, and crushes the book. Same pattern on the remaining tasks (Appendix A.4).
Replanning frequency: ~25 Hz on an A5000 (control tick 40 ms) vs ~7 Hz for baselines that pay the full GR00T pipeline latency per call.

Why it’s interesting

Sits directly next to Real-Time Robot Execution with Masked Action Chunking (REMAC) as the architectural + scheduling answer to the async-inference problem where REMAC is the training-recipe answer, and both cite Train-Time RTC as the strongest prior baseline. REMAC’s fix — LoRA + prefix-mask + self-conditioning curriculum + residual-alignment loss — leaves the DiT structure and the standard multi-step sampler intact; πR² keeps the base flow-matching objective but rewrites the DiT’s AdaLN as per-position and rewrites the noise schedule into a delay-parameterized staircase. The two are complementary in principle (πR² does not do anything about intra-chunk-inconsistency-within-the-executed-prefix, which is REMAC’s specific target; REMAC does not disentangle a fast/slow channel or amortize denoising across calls). Neither combines the two — one obvious future direction.

The proprioception-fast / vision-slow split is also the sharpest concrete instance of the Jitendra Malik: don't let CV researchers in robotics skip the sensorimotor level sensorimotor counter-position landing inside a mainstream flow-matching VLA stack: not by adding a new modality (as Tactile-Reactive Dexterous Hand: High-Frequency Physical Interaction does with tactile) but by structurally elevating the modality that was already there (proprioception, including fingertip force) to a per-tick refresh rate that vision never gets. On the LLM Inference Efficiency board, it’s a robotics-side instance of the hide latency via structural decoupling pattern — sibling to Sunday Robotics’ finding (Sunday Robotics finds on-device VLA inference beats cloud during ACT-2 eval (Cheng Chi)) that home-VLA cloud inference is tail-latency-limited by the network hop rather than by per-step compute, but attacking the same problem from the model side rather than the deployment side. The paper reports 0.30 s → 40 ms per replan on an A5000 without shrinking the backbone, model or context — the lever is scheduling and cache invalidation, not compression.