AI Performance Engineering — curated resource list for GPU perf engineering and production inference

TL;DR

A curated resource list (MIT-licensed) for learning AI performance engineering, ordered from a single inference request through kernel optimization, inference engines, distributed serving, and current-generation hardware. Under a documented source policy: entries must be the paper that introduced a mechanism, the specification/official docs that define it, the repository that implements it, or an implementer report with code + measurements + baselines. Performance claims require hardware, workload, precision, baseline, and correctness method — otherwise the number is omitted. Maintained by Wafer AI as the reading path for GPU-perf-engineering hires; the “Frontier” section (verified 2026-08-23) tracks watchlist items (Rubin, MI400, agentic scheduling on production traces, real-time voice/video serving, inference ASICs) kept separate from the stable core.

Key claims

The recommended entry sequence (“Start here: the minimum mental model”) is: (1) All About Transformer Inference — Chapter 7 of How To Scale Your Model — one request from prefill through decode with batching, KV memory, parallelism; (2) Attention Is All You Need; (3) CUDA C++ basics; (4) Programming Massively Parallel Processors (Hwu, textbook); (5) the Berkeley Roofline paper; (6) Transformer Inference Arithmetic (kipply); (7) Efficiently Scaling Transformer Inference (MLSys 2023); (8) Etalon (TTFT/TPOT/goodput/latency SLOs) [§“Start here”].
Kernel optimization structured as: foundational exercises (matrix transpose, parallel reduction, decoupled-look-back scan, online softmax) → matrix multiplication (Volkov 2008, CuTe GEMM tutorial, CUTLASS 3.x, DeepGEMM) → direct implementer worklogs (siboehm CUDA MMM, Aleksa Gordic H100 matmul, cudaforfun H100 worklog, Colfax TMA tutorial) → tensor-cores and low-precision (OCP FP8/MX specs, NVIDIA TransformerEngine, Blackwell tcgen05) → attention (FlashAttention 1/2/3/4, FlashInfer) [§“Kernel optimization”].
Programming-model coverage splits by hardware stack: Triton (paper, guide, repo); CUTLASS + CuTe + CUDA Tile (layout algebra, GEMM tutorial, pipeline docs, Tile IR + repo); ROCm Composable Kernel / AITER / HipKittens for AMD; Pallas for JAX GPU+TPU; NKI for AWS NeuronCore [§“Programming models and profiling”].
Inference-engine section maps to the wiki’s LLM Inference Efficiency cluster axis-by-axis: scheduling and continuous batching (Orca, PagedAttention/vLLM, Sarathi-Serve, SGLang, TensorRT-LLM); KV cache systems (GQA, DeepSeek-V2 MLA, KIVI, CacheGen, Mooncake); quantization (GPTQ, SmoothQuant, AWQ); speculative decoding (Leviathan, DeepMind speculative sampling, Medusa, EAGLE); structured decoding (Guiding LLMs, XGrammar) and fairness; long-context (Ring Attention, MInference, Native Sparse Attention) [§“Inference engines”].
Distributed inference: parallelism/collectives/topology (Megatron-LM, NCCL, GB200 NVL tuning, UALink 1.0, Ultra Ethernet 1.0.3); mixture-of-experts serving (DeepSeek-V3, DeepEP, EPLB, MegaScale-Infer); prefill/decode disaggregation (DistServe, Splitwise, Mooncake, NIXL, Dynamo); production systems (Clockwork, ServerlessLLM, Gateway API Inference Extension, llm-d); serving benchmarks (MLPerf Inference, Etalon, ServeGen, BurstGPT, MLPerf Endpoints) [§“Distributed inference”].
Hardware section is organized so each architecture is read alongside its ISA or tuning guide, with an explicit warning that vendor peak numbers are not performance measurements. NVIDIA Blackwell (architecture brief, tuning guide, CUTLASS Blackwell docs); AMD CDNA 4 (whitepaper, ISA, MI350 counters); Google TPU (v1 analysis, v4, Ironwood/v7, Pallas TPU model); AWS Trainium (Trainium/Inferentia2 arch, Trainium3, NKI perf guide) [§“Current hardware”].
“Frontier” section is deliberately timestamped (verified 2026-08-23) and separated from the core list because evidence changes quickly. AI-generated-kernel entries include KernelBench, KernelBench-Verified, SOL-ExecBench; watchlist explicitly names Rubin/Rubin CPX, AMD MI400/CDNA 5/Helios, session-aware and agentic scheduling on public production traces, real-time voice/video serving with complete quality+latency metrics, inference ASICs, processing-in-memory, analog compute, photonic compute — “pending reproducible deployments” — and individual AI kernel agents “that have not been rerun on a hardened evaluator” [§“Frontier”, “Watchlist”].
Source policy: a core-list source must be (a) the paper that introduced the mechanism, (b) the specification or official documentation that defines it, (c) the repository that implements it, or (d) a direct implementer report with code + measurements + enough detail to reproduce. Performance claims need hardware, workload, precision, baseline, and correctness method; otherwise the number is omitted [§“Source policy”].

Method

The repo is a single README + CONTRIBUTING policy. Structure: seven ordered sections (Start-here → GPU fundamentals → Kernel optimization → Programming models and profiling → Inference engines → Distributed inference → Current hardware) plus a timestamped Frontier section. Each entry is a one-line description linking to the primary source (paper URL, official doc, repo, or implementer worklog). No commentary paragraphs; the position of an entry in the ordering carries the pedagogical claim. The GPU Mode lectures (github.com/gpu-mode/lectures) are cited once at the end of Start-here as a “practical companion.”

Results

Not applicable — this is a curated bibliography, not an experimental artifact. The value is (a) the ordering + source-policy discipline, (b) coverage of the AMD and TPU stacks alongside NVIDIA (most similar lists are CUDA-only), (c) the explicit separation of “stable core” from timestamped “frontier” so the reader knows which links are load-bearing vs speculative, and (d) the “vendor peak numbers are not performance measurements” reminder attached to the hardware section.

Why it’s interesting

The repo is the closest thing on the wiki to a reading list companion to the LLM Inference Efficiency and IO-Aware Kernel Design concept clusters — most of the primary sources cited on those concept pages appear in this list, and the ordering (single-request math → kernel → engine → distributed → hardware) matches the order in which the wiki’s own inference-efficiency arguments are typically constructed. Position 1 in the “Start here” sequence is All About Transformer Inference — Chapter 7 of How To Scale Your Model, filed as a sibling in this ingest. The source-policy discipline (specifically requiring baseline + hardware + workload + correctness for any performance claim) is exactly the methodological standard Revisiting RaBitQ and TurboQuant: A Symmetric Comparison of Methods, Theory, and Experiments flags as the missing ingredient in current inference-efficiency literature — an outside signal that the discipline the wiki has been building up in its LLM Inference Efficiency TL;DR (baseline parity as a first-class dimension) is being adopted as a curation policy elsewhere. Also complements Inside TPU and GPU Clusters: The Anatomy of Collective Communication as a broader entry point into the same TPU/GPU distributed-serving terrain.