Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI

TL;DR

Architect Labs reports Redwood, a tile-based near-memory-dataflow AI accelerator for single-batch, low-power, ultra-low-latency inference, whose entire software-to-silicon flow — performance model, RTL, UVM environments, formal proofs, firmware, drivers, and compute kernels — was generated end-to-end by their AI system (ALP) in under two weeks from a two-architect specification, with no human intervention below the spec. Every block reached 95% code and functional coverage; the Nano configuration was deployed to an AMD Versal VPK180 FPGA and runs Qwen3-0.6B, Llama, and Kimi. Projected onto a Samsung 8 nm-class process comparable to NVIDIA Jetson Orin Nano, Redwood Nano is reported at 1.75× decode throughput at 1.9× lower power, i.e. 3.4× perf/watt against a measured Jetson baseline. Qwen running on Redwood in turn helped design the next Redwood generation, staged as an early recursive-self-improvement demonstration.

Key claims

The full chip design cycle — architectural definition, RTL, UVM, formal proofs, firmware, kernels, and FPGA bring-up — was generated end-to-end by the Architect Labs AI system in under two weeks from a two-architect specification, with each architectural change regenerated, reverified, and redeployed to hardware in under 48 hours [§V, Fig. 11].
Every Redwood block reached 95% code and functional coverage via commercial EDA tools + a proprietary formal engine + hardware-in-the-loop; the first RTL drop from simulation to FPGA was reported with zero downstream bugs [§V.A].
On the AMD Versal VPK180 FPGA at 250 MHz, Redwood Nano measures 12.1 avg tokens/s on Qwen3-0.6B decode (LPDDR4, 16 GB/s DRAM BW) against 28 tokens/s on Jetson Orin Nano at 1020 MHz (LPDDR5, 68 GB/s) [Table I].
Roofline analysis of one Qwen3-0.6B decoder layer at context length 128 shows decode is strongly memory-bound: 44.65 ms of aggregate DRAM service vs 12.29 ms of arithmetic service per token, giving an architectural ceiling of 21.73 tokens/s on the FPGA and a conservative fully-serialized bound of 17.56 tokens/s [Table II, §IV.A].
Projected onto a Samsung 8 nm-class ASIC at 1 GHz with Jetson-comparable memory bandwidth, Redwood Nano is estimated at 49 avg tokens/s vs Jetson’s 28, at 1.335 W vs 2.59 W, giving 36.7 vs 10.8 tokens/s/W — a 3.4× perf/watt gain in ~2.88 mm² [Table III, §IV.B].
Architecture is a tile-based spatial-dataflow mesh with a global control core (MCU), per-tile RISC-V control cores (CRV), matrix (CMXM) and vector (CVXM) engines co-designed for transformer kernels (FlashAttention, GEMM, GEMV), and a credit-based NoC with broadcast/multicast and table-based stream redirection; DMA back ends are AXI4 today but retargetable to ACE/CHI [§II, Fig. 1-2].
Front-end / back-end split within each tile lets the FE run at a slower clock domain and shut down during kernel execution, and lets the CRV enqueue Core Task Manager (CTM) tasks that then execute independently — moving scheduling into software and reducing arbitration complexity in the mesh [§II.A-B, Fig. 4].
A CTM-to-CTM messaging fabric allows tiles and DMA engines to synchronize control flow (double-buffering, prefetch, out-of-order compute) without involving the CRV or MCU [§II.B, Fig. 5-6].
The programming model dispatches “DP sets” (MCU programs) and “kernel sets” (per-tile programs) loaded into ITCM; the host writes a dispatch ID + operands and the MCU orchestrates DMA/tile launches until completion [§III, Fig. 7].
AI-driven microarchitectural exploration searches a space “an order of magnitude larger” than a human team’s for units like the SIMD engine, generating candidate RTL with different control paths, datapaths, and state machines — not just bit-width or register-arrangement tweaks — while continuously optimizing performance/area/timing/coverage [§V.B, Fig. 13-14].
Firmware and kernels for Qwen inference were written and tested by the AI system against ALP projections, cycle-accurate RTL simulation, or FPGA builds, using an in-house emulation environment that multiplexes FPGA access across “hundreds of concurrent agents” [§V.C].
Deploying Qwen3 on Redwood as an inference endpoint inside the AI system enabled the Qwen-hosted-on-Redwood model to discover multiple timing improvements and kernel optimizations for its own operations at near-zero inference cost, staged as an early recursive-self-improvement loop [§V.C, thread posts].
The SIMD engine uses the FlashAttention-4 emulated-softmax algorithm to reuse existing SIMD resources for softmax instead of dedicated area [§II.A].

Method

Redwood is an N×M mesh of identical tiles surrounded by edge DMA engines, connected to external memory via a global DMA fabric and to on-chip West/North/East last-level SRAM banks. Each tile pairs a RISC-V control core (CRV) with matrix (CMXM: systolic GEMM/GEMV) and vector (CVXM: SIMD/transpose/FP activations) engines feeding a 512 KB local scratchpad (CMEM). A front-end / back-end split lets sparse control run in a slower clock domain (and gate off during kernel execution) while the back-end handles high-bandwidth compute. A Core Task Manager (CTM) inside each tile bridges the CRV to the functional units, supports task-ID-based fencing and out-of-order completion, and communicates with peer CTMs (in tiles and DMA engines) over an on-die messaging fabric so scheduling and prefetching are expressed as message flows rather than centralized arbitration. The programming model separates MCU-hosted “Dispatch Programs” (which configure routing tables, DMAs, and launch kernels) from tile-hosted kernels, both grouped into sets loaded into ITCM to amortize initialization.

The Architect Labs Platform (ALP) collapses the traditional sequential ASIC lifecycle (architecture → RTL → verification → firmware → tapeout) into a single automated flow: from a human-authored specification, ALP generates the performance model, RTL, UVM environments, SVA assertions, formal proofs, firmware, drivers, and compute kernels in parallel, with humans maintaining ALP itself and adjusting the specification based on functional/area/timing/power/coverage feedback. Verification is fully automated — testbenches, tests, and formal artifacts are AI-generated with no human DV participation. Microarchitectural exploration searches a large candidate space per hardware block (SIMD, matrix engines) with continuous PPA and coverage feedback. Firmware and kernels are co-developed before RTL/verification collateral exists, and tested against ALP projections, cycle-accurate RTL simulation, and FPGA builds via a custom emulation environment that multiplexes FPGA access across hundreds of concurrent agents.

Results

Measured on VPK180 FPGA at 250 MHz on Qwen3-0.6B: 12.1 avg tokens/s (LPDDR4, 16 GB/s BW) [Table I]. Roofline ceiling at that configuration is 21.73 tokens/s [§IV.A]. Projected onto Samsung 8 nm-class ASIC at 1 GHz with Jetson-comparable memory bandwidth: 49 avg tokens/s at 1.335 W in ~2.88 mm² vs the measured Jetson Orin Nano baseline of 28 tokens/s at 2.59 W — 1.75× perf, 1.9× lower power, 3.4× tokens/s/W [Table III]. Design timeline: two weeks from spec to complete RTL + verification + firmware + kernels + timing closure with 95% coverage across all blocks, plus a third week to bring target LLM workloads online; commit history reports a peak of 115 merge commits in one day during workload bring-up [§V, Fig. 11-12]. Verification: to date the flow has not seen a bug missed in verification but revealed in hardware, and the first RTL drop from sim to FPGA was reported bug-free [§V.A].

Why it’s interesting

Redwood is the first filed wiki entry where an AI-for-AI-research loop closes through silicon design and physical hardware bring-up rather than architectures (AlphaGo Moment for Model Architecture Discovery), papers (FARS: Fully Automated Research System), training-script knobs (Scaling Karpathy's Autoresearch: What Happens When the Agent Gets a GPU Cluster), or the AI-scientist agent itself (AIDE²: First Evidence of Recursive Self-Improvement) — extending AI-for-AI Research to a new granularity comparable to ENPIRE: Agentic Robot Policy Self-Improvement in the Real World‘s closed-loop robot-policy improvement, but with the RTL/UVM/firmware artifact stack replacing the robot rollout as the physical ground truth. The recursive-self-improvement claim — Qwen-on-Redwood proposing kernel and timing improvements for the next Redwood generation — is a concrete instantiation of the same “model improves the hardware that runs it” story sketched in Kimi K3 Technical Report — Open Frontier Intelligence‘s chip-design demo, but this one ships as a paper with measured FPGA numbers and a projected 3.4× perf/watt ASIC target. The tile / near-memory / spatial-dataflow architecture and the explicit reuse of IO-Aware Kernel Design primitives (FlashAttention-4’s emulated softmax on shared SIMD, tile-local scratchpad, DMA-orchestrated data staging) also make Redwood a datapoint on how hardware/software co-design shifts when a single AI system optimizes both sides under one objective.