Jeff Holden announces Atomic Machines and the Matter Compiler — PrimeSwitch PS-150 micro-machine power relay for AI data centers

TL;DR

Jeff Holden (Amazon’s 10th engineer, Amazon Prime builder, Uber’s first CPO) emerges from six years in stealth with Atomic Machines ($250M raised) and introduces the Matter Compiler — an AI-native, all-digital manufacturing system that builds working micro-machines directly from code with no molds, masks, or fixed tooling. The first product is PrimeSwitch PS-150, a bistable electromechanical power relay with 200 µΩ on-resistance, 150 A continuous current in a 9.5 × 3 mm hermetic package, that opens in 50 µs with 1,500 V galvanic isolation (~1,000× faster than a conventional contactor). Target market: the ongoing transition of AI data centers to 800 VDC power distribution, where fault energy arrives faster than mechanical protection can respond and solid-state alone cannot galvanically isolate.

Key claims

The Matter Compiler closes an intent→result loop: every manufacturing operation is followed by precision metrology, a part only proceeds if in spec, and the AI runs its own hardware-in-the-loop experiments to generate training data continuously — “at maturity: prompt-to-product” [tweet thread, post 3].
Scope target is micro-machines: 3D devices with moving parts, multi-material subsystems, features down to single-digit microns — the regime between conventional machining (limited to ~tens of microns) and semiconductor fab / MEMS (locked to a narrow process window and years of per-device process work) [tweet thread, posts 4-5].
PrimeSwitch PS-150 specs: 200 µΩ on-resistance, 150 A continuous, 9.5 mm × 3 mm hermetic package, 50 µs open time, 1,500 V galvanic isolation, zero holding power, shipping to early-access customers [tweet thread, post 6].
Market thesis: 800 VDC AI data center fault energy arrives in microseconds and DC arcs do not self-extinguish; mechanical protection is milliseconds too slow and pure solid-state carries ohmic loss on every amp and cannot isolate — a hybrid breaker with solid-state bypass + PrimeSwitch as the isolation element lets “the silicon interrupt, the metal carry and isolate, the breaker never arc” [tweet thread, posts 7-8].
First public demo at Open Compute Project Global Summit, San Jose, Oct 12-15 2026 [tweet thread, post 9].

Method

Atomic Machines frames the Matter Compiler as a universal grid of 7 physical domains × 2 purposes (deliver energy/matter, or encode information), of which semiconductor fab has mastered exactly one cell. MEMS has coaxed a few additional devices (accelerometers, gyros, micro-mirrors, inkjet nozzles) out of the semi toolset over decades, but the rest of the grid requires processes and materials semi fab was never built for — the Matter Compiler is pitched as the manufacturing stack that covers the remaining cells, with code (not tooling) as the device specification. Design intelligence and manufacturing are built together: an AI loop sits inside the physical system, so every build generates measurements that feed both device design and future Matter Compiler input generation. The named reference is Neal Stephenson’s The Diamond Age.

Results

PrimeSwitch PS-150 is the first product shipping to evaluation customers. Headline deltas versus incumbent power switching for 800 VDC AI data center use:

vs. electromechanical contactor: ~1,000× faster open time (50 µs vs. ~tens of ms); hermetic 9.5 × 3 mm package instead of palm-sized.
vs. solid-state (SSR / SiC): provides true galvanic isolation (1,500 V) and zero holding-power ohmic loss, while matching metal-to-metal conduction efficiency (200 µΩ) — i.e. no steady-state heat penalty per amp carried.
Capability provenance: the device “exists because the Matter Compiler exists” — no semiconductor fab can process its materials or assemble its moving parts [tweet thread, post 9].

$250M total raised over six stealth years; investor list per press coverage includes OneIM, Gigafund, XTX Ventures, KAS Venture Partners, Valor Equity Partners, Tru Arrow Partners, Construct Capital, Sozo Ventures, and the Regents of the University of California (not stated in the thread itself).

Why it’s interesting

This is an infrastructure announcement rather than an ML result, but it’s directly relevant to the physical substrate the Luma research team’s compute runs on. The AI data center 800 VDC transition shows up in training-infra reporting around this filing window — see Previewing the Model Hardware Standard on hardware-standard work and Our eighth generation TPUs: two chips for the agentic era (TPU 8t and TPU 8i) for the eighth-gen TPU rollout, both of which assume high-voltage DC distribution upstream of the rack. More structurally, the “AI-native manufacturing with HIL metrology in the training loop” framing rhymes with the self-improving-system threads filed under AI-for-AI Research (e.g. The Last AI Built by Humans: Toward Genuine Recursive Self-Improvement, AIDE²: First Evidence of Recursive Self-Improvement) — same pattern applied to atoms rather than code. Worth watching as a signal about how the AI-infra buildout is pulling adjacent hardware categories (power switching, cooling, interconnect) into AI-native-manufacturing timelines.